The minimum dimension that a given photolithography process can resolve is alternatively called the minimum feature size or the critical dimension. The feature size is a parameter of interest as reductions in the feature size tend to improve speed performance of the IC. The feature size of a printed integrated circuit (IC) is not uniform. The printing process results in slight variation of the feature size from lot-to-lot, from wafer-to-wafer, and from device to device within each wafer. As a result, programmable ICs, such as field programmable gate arrays (FPGAs) and other programmable logic devices, may experience variations in static power and circuit delay due to variations in the manufacturing process.
As circuit designs continue to increase the speed and power efficiency requirements of target devices, it is increasingly important for developers to simulate and test circuit designs on target devices using precise power and delay specifications prior to realization. Many programmable IC vendors, such as Xilinx, Inc., measure switching speed of several printed devices of a product design to determine a voltage or delay specification that can be guaranteed to designers. This is referred to as a timing specification. The timing specification is sometimes referred to as a speedfile or a performance guarantee, and such terms are used interchangeably herein.
Switching speed is not uniform throughout a particular die or from die-to-die. Some manufacturing variations may consistently result in circuit elements in different regions of a die having different switching speeds. These types of variations are referred to as systematic variations. Other manufacturing variations are unpredictable and are characterized as random variations. Random variations may cause variation between dies for a particular location. Random variations may be due to lithography, masking or some other process required in the manufacturing of the integrated circuit devices. Systematic variations may be accurately represented and accounted for by an average of measured delay values at various locations on the die. In contrast, random variations result in a wider distribution of measurements for each location that are gathered from a large number of dies. Random variations may not be accurately represented by a mean of measured values.
Due to the measured differences between devices caused by random variations in the die, the average delay measurements must be de-rated. The timing data for the slowest elements in the slowest die is used to characterize the devices. However, such a characterization may be unduly pessimistic and may not accurately reflect the speed of the device. The percentage of devices that do not violate the guaranteed delays indicated by a timing specification is known as a timing yield. Because conventional timing characterization methods do not account for the fact that certain resources of a device may be consistently faster than others due to systematic variation, conventional speed characterization methods lead to pessimistic resource delay specifications.
Due to random type variations in the die from device to device, in order for the guaranteed specification to apply to a majority of the devices, the parameters of the specification are offset to include a certain amount of headroom above the average. The offset of a timing specification is typically chosen for a particular timing yield to be guaranteed by a vendor and is important to delivering high-quality devices as well as for maintaining low cost for devices. The particular timing yield is also referred to as the target timing yield or selected timing yield, and such terms are used interchangeably herein. For example, measurements may indicate that the majority of product devices can operate on average at or above 110 megahertz (MHz) at 1V operating voltage, but a small percentage of the devices will operate as low as 102 MHz at the same voltage. The specification may offset an average speed of 110 MHz by a headroom of 10 MHz to ensure that an acceptable percentage of devices perform as indicated in the specification. The presence of process variations degrades the performance and power specifications that manufacturers can guarantee to customers. The larger the amount of random variation, the larger the specification is offset by a headroom. Because of the included headroom, many printed devices in a product design are capable of performing with better voltage and delay parameters than those guaranteed in the vendor product specification.
The present invention may address one or more of the above issues.